Semiconductor technologies are continually progressing to smaller feature sizes, for example down to feature sizes of 28 nanometers, 20 nanometers, and below. Various integrated circuit (IC) features with small feature sizes are formed on a semiconductor wafer by various techniques. For example, double patterning is used to form a plurality of features with small pitch. However, there is no effective way to fabricate a irregular pattern by double patterning.
Therefore, what is needed is a method and a photomask structure to provide effective IC design and fabrication for the advanced IC technologies addressing the above problems.